This invention relates to testing of integrated circuits, and more specifically to a method for testing faults in programmable logic devices.
Programmable logic devices exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAS) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called the field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost. A FPGA typically includes an array of configurable logic blocks (CLBS) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by programmable routing resources (such as single length, intermediate length and long interconnect lines) that are controlled by a plurality of programmable interconnection points (PIPs). The CLBs, IOBs, and the PIPs are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBS, IOBS, and PIPs are configured. The configuration data is typically organized into frames. The configuration bitstream may be read from an external memory (e.g., an external PROM). The collective states of the individual memory cells then determine the function of the FPGA.
FPGAs are used by many users to implement a large number of circuits. These circuits can use any CLBs, IOBs, and interconnect lines in a FPGA. A product may malfunctions if any of these resources have defects. Thus, it is important to test a FPGA to make sure that all of these components are free of defects.
In IC technology, testing is an experiment in which an IC is exercised by applying a test vector to some of the inputs of the IC. The resulting response signals are analyzed to determine whether defects may be present in the IC. One way to test the interconnect lines is to turn on the appropriate PIPs to generate a chain of interconnect lines so that both ends of the chain are accessible externally. A test vector is then applied to the input end and the result measured at the output end. In order to test all the interconnect lines, a large number of chains need to be constructed and tested.
The chain is constructed by turning on appropriate PIPs. FIG. 1 shows an example of a chain 12 by turning on PIPs 16a-16d. A large number of similar chains need to be constructed, and associated PIPs turned on, in order to test all the interconnect lines.
Broadly speaking, there are two kinds of faults of interest: open fault and short fault. An open fault occurs when there is one or more unintended discontinuity on an interconnect line (or a series of connected interconnect lines). Chain 12 of interconnect lines is often used to test open faults. The connection of chain 12 is controlled by a plurality of PIPs, such as PIPs 16a-16d. Each PIP is controlled by a configuration memory (such as memories 14a-14d). When all the memories are at an ON state, chain 12 becomes conductive if there is no unintended discontinuity. However, if there is an open fault at an unintended point along chain 12, this chain becomes non-conducting. The open fault in chain 12 can be detected by sending a signal at a first end of chain 12, and determining whether the signal is detected at a second end. If chain 12 has an open fault, the signal would not pass from the first end to the second end.
In FIG. 1, the set of PIPs that are in the ON state, thus used in construction chain 12, are called the xe2x80x9cused set.xe2x80x9d In conventional testing, a large number of configurations, each having a different used set, is loaded into a FPGA and then tested. All the PIPs in the used set in each configuration are turned on, and the open faults, if any, are detected by the above-mentioned measurement.
It is more difficult to measure short faults. A short fault occurs when two unconnected lines are shorted (i.e., connected) in one or more unintended places. The unintended connection that gives rise to the short fault may pass through a large area of a programmable logic device. When a signal is sent to one of the two unconnected lines, the signal may undergoes a large number of transformations when it reach the other unconnected line. As a result, it is more difficult to detect short faults.
One method to measure short fault is the so called xe2x80x9cIDDQxe2x80x9d (VDD supply current quiescent) method. This method relies on the fact that when a complementary CMOS logic gate is not switching, it draws no DC current (except for leakage). When a fault occurs, for some combination of input conditions a measurable DC current, Idd, will flow. Testing consists of applying appropriate test signals, allowing the signals to settle, and then measuring the Idd. However, the combination of line pairs to be tested and short faults that may be activated in a large sized FPGA is enormous. Thus, the IDDQ method for detecting short faults is not reliable or practical.
What is needed is a simple yet reliable method for testing short faults.
The present invention involves a new method to test faults in programmable logic devices. Line segments under test in the programmable logic device are connected together to form one or more chains. These line segments are called the xe2x80x9cused lines.xe2x80x9d Line segments in the device that are not associated with one of these chains are called xe2x80x9cunused lines.xe2x80x9d A PIP that is incident with a used line at one end and incident with an unused line at another end is called a xe2x80x9cneighborxe2x80x9d PIP. An unused interconnect line segment attached to a neighbor PIP is called a xe2x80x9cneighbor line.xe2x80x9d In the present invention all the neighbor lines should be tied to a known state. A test vector is applied to the programmable logic device. The state of the line under test is measured. If it is different from the known state, short fault is not likely to occur.
This method is especially efficient in finding short faults in a FPGA. This is because the majority of resources in a FPGA is normally not used. As a result, a large number of resources can be tested at the same time.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.